The technology described in this disclosure relates generally to integrated circuits and more particularly to a system for protecting a circuit from an electrostatic discharge (ESD) voltage.
Gate-all-around (GAA) nanowire channel field-effect transistors (FETs) may enable feature scaling beyond current planar complementary-metal-oxide semiconductor (CMOS) technology. Nanowire channel FETs may also be of interest due to their electrostatics, which may be superior to those of conventional FET devices. The fabrication of nanowire channel FETs may include generating a collection of nanowires and placing them where desired (e.g., a bottom-up approach) or may include various lithographic patterning procedures (e.g., a top-down approach).